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EP13E7 Series Oscillator
Quartz Crystal Clock Oscillators XO (SPXO) LVCMOS (CMOS) 3.3Vdc 4 Pad 2.5mm x 3.2mm Ceramic Surface Mount (SMD)

Revision  H  12/11/2012

Electrical Specifications

Nominal Frequency 3.300MHz to 100.000MHz
Some frequencies within this range may not be available.
Frequency Tolerance/Stability (Inclusive of all conditions: Calibration Tolerance at 25°C, Frequency Stability over the Operating Temperature Range, Supply Voltage Change, Output Load Change, First Year Aging at 25°C, 260°C Reflow, Shock, and Vibration)
±100ppm Maximum
±50ppm Maximum
±25ppm Maximum
Operating Temperature Range -20°C to +70°C
-40°C to +85°C
Supply Voltage (VDD) 3.3VDC ±5%
Input Current 12mA Maximum over Nominal Frequency of 3.3MHz to 25MHz
17mA Maximum over Nominal Frequency of 25.000001MHz to 75MHz
22mA Maximum over Nominal Frequency of 75.000001MHz to 90MHz
25mA Maximum over Nominal Frequency of 90.000001MHz to 100MHz
Output Voltage Logic High (VOH) IOH = -8mA
90% of VDD Minimum
Output Voltage Logic Low (VOL) IOL = +8mA
10% of VDD Maximum
Duty Cycle Measured at 50% of waveform
50 ±5(%)
Rise Time/Fall Time Measured at 20% to 80% of Waveform
6nSec Maximum over Nominal Frequency of 3.3MHz to 50MHz
4nSec Maximum over Nominal Frequency of 50.000001MHz to 75MHz
2nSec Maximum over Nominal Frequency of 75.000001MHz to 100MHz
Load Drive Capability 30pF Maximum over Nominal Frequency of 3.3MHz to 50MHz
15pF Maximum over Nominal Frequency of 50.000001MHz to 100MHz
Output Logic Type CMOS
Pin 1 Connection Power Down
Tri-State
Pin 1 Input Voltage (Vih and Vil) 90% of VDD Minimum or No Connect to Enable Output, 10% of VDD Maximum to Disable Output
Standby Current 30µA Maximum (Pin 1 = Ground)
Disable Current 8mA Maximum (Pin 1 = Ground)
Absolute Clock Jitter 350pSec Maximum over Nominal Frequency of 3.3MHz to 24.999999MHz
200pSec Maximum over Nominal Frequency of 25MHz to 100MHz
Aging (at 25°C) ±5ppm/year Maximum
Storage Temperature Range -55°C to +125°C
Start Up Time 10mSec Maximum