Log On  |  714-433-1200  |  Email Customer Support

EQUA33 Series Oscillator
Temperature Compensated Voltage Controlled Quartz Crystal Clock Oscillators TCVCXO LVCMOS (CMOS) 3.3Vdc 6 Pad 2.5mm x 3.2mm Ceramic Surface Mount (SMD)

Revision  A  09/09/2015

Electrical Specifications

Nominal Frequency 10.000MHz to 200.000MHz
Some frequencies within this range may not be available.
Frequency Stability Inclusive of Operating Temperature Range, at VDD=3.3VDC, at VC=1.5VDC
±5.0ppm Maximum
±3.0ppm Maximum
±2.5ppm Maximum
±2.0ppm Maximum
±1.5ppm Maximum
±1.0ppm Maximum
Frequency Stability vs. Frequency Tolerance At 25°C ±2°C, at VDD=3.3VDC, at VC=1.5VDC ±0.1VDC, Pre-Reflow
±2.0ppm Maximum
±1.5ppm Maximum
±1.0ppm Maximum
Frequency Stability vs. Input Voltage ±0.2ppm Maximum (±5%)
Frequency Stability vs. Load ±0.2ppm Maximum (±2pF)
Frequency Stability vs. Reflow ±1.0ppm Maximum (at 25°C, 24 hours after reflow, 1 time)
Frequency Stability vs. Aging ±1ppm/Year Maximum (at 25°C)
Operating Temperature Range 0°C to +50°C
-10°C to +60°C
0°C to +70°C
-20°C to +70°C
-30°C to +60°C
-30°C to +75°C
-30°C to +85°C
-40°C to +85°C
Supply Voltage 3.3VDC ±5%
Input Current Unloaded
20mA Maximum over Nominal Frequency of 10MHz to 50MHz
25mA Maximum over Nominal Frequency of 50.000001MHz to 100MHz
30mA Maximum over Nominal Frequency of 100.000001MHz to 200MHz
Output Voltage Logic High (Voh) IOH = -4mA
90% of VDD Minimum
Output Voltage Logic Low (Vol) IOL = +4mA
10% of VDD Maximum
Rise/Fall Time Measured at 10% to 90% of Waveform
3nSec Maximum
Duty Cycle Measured at 50% of Waveform
50 ±5(%)
Load Drive Capability 15pF Maximum
Output Logic Type CMOS
Control Voltage 1.5VDC ±1.0VDC
Frequency Deviation ±8ppm Minimum
Linearity 10% Maximum
Transfer Function Positive Transfer Characteristic
Modulation Bandwidth Measured at -3dB
10kHz Minimum
Input Impedance 1MOhms Minimum
Phase Noise Click to Open Phase Noise Table
Output Control Function Output Enable (OE)
Output Control Input Voltage Logic High (Vih) 90% of VDD Minimum or No Connect to Enable Output
Output Control Input Voltage Logic Low (Vil) 10% of VDD Maximum to Disable Output (High Impedance)
Output Enable Time 100nSec Maximum
Output Disable Time 50nSec Maximum
Output Enable Current Without Load (Pin 2 = Ground)
15mA Maximum
RMS Phase Jitter Click to Open RMS Phase Jitter Table
Period Jitter (Deterministic) 0.2pSec Typical
Period Jitter (Random) 2pSec Typical
Period Jitter (RMS) 3pSec Maximum
Period Jitter (pk-pk) 30pSec Maximum
Start Up Time 10mSec Maximum
Storage Temperature Range -55°C to +125°C