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EQVE13 Series Oscillator
Voltage Controlled Quartz Crystal Clock Oscillators VCXO LVDS (DS) 3.3Vdc 6 Pad 5.0mm x 7.0mm Ceramic Surface Mount (SMD)

Revision  A  07/30/2014

Electrical Specifications

Nominal Frequency 10.000MHz to 625.000MHz
Some frequencies within this range may not be available.
Frequency Tolerance/Stability Inclusive of all conditions: Calibration Tolerance (at 25°C), Frequency Stability over the Operating Temperature Range, Supply Voltage Change and Output Load Change
±50ppm Maximum
Operating Temperature Range 0°C to +70°C
-20°C to +70°C
-40°C to +85°C
Aging at 25°C ±2ppm Maximum First Year, ±10ppm/10 Years Maximum
Supply Voltage 3.3VDC ±5%
Input Current 25mA Maximum
Output Voltage Logic High (VOH) 1.425VDC Typical
Output Voltage Logic Low (VOL) 1.075VDC Typical
Differential Output Error (dVod) 50mVDC Maximum
Differential Output Voltage (Vod) 200mVDC Minimum, 350mVDC Typical, 454mVDC Maximum
Offset Voltage (Vos) 1.125V Minimum, 1.250V Typical, 1.375V Maximum
Duty Cycle Measured at 50% of Waveform
50 ±10(%)
50 ±5(%)
Rise Time/Fall Time Measured at 20% to 80% of Waveform
500pSec Maximum
Offset Error (dVos) 50mVDC Maximum
Load Drive Capability 100 Ohms Between Output and Complementary Output
Output Logic Type LVDS
Absolute Pull Range Inclusive of all conditions: Calibration Tolerance (at 25°C), Frequency Stability over the Operating Temperature Range, Supply Voltage Change, Output Load Change, Shock, Vibration, and 10 Year Aging over the Control Voltage (Vc)
±30ppm Minimum
±50ppm Minimum
Control Voltage Test Condition for APR
0.3VDC to 3.0VDC
Control Voltage Range 0.0VDC to VDD +0.6VDC
Linearity 5% Typical, 10% Maximum
Transfer Function Positive Tranfer Characteristic
Modulation Bandwidth Measured at -3dB, Vc = 1.65VDC
10kHz Minimum
Input Impedance 500kOhms Minimum
Input Leakage Current 10µA Maximum
Phase Noise Click to Open Phase Noise Table
Output Control Function Output Enable (OE)
Output Control Input Voltage Logic High (Vih) 90% of VDD Minimum or No Connect to Enable Output and Complementary Output
Output Control Input Voltage Logic Low (Vil) 10% of VDD Maximum to Disable Output and Complementary Output (High Impedance)
Output Enable Time 100nSec Maximum
Output Disable Time 50nSec Maximum
Output Enable Current Without Load (Pin 2 = Ground)
18mA Maximum
RMS Phase Jitter Click to Open RMS Phase Jitter Table
Period Jitter (Deterministic) 0.2pSec Typical
Period Jitter (Random) 2pSec Typical
Period Jitter (RMS) 3pSec Maximum
Period Jitter (pk-pk) 25pSec Maximum
Storage Temperature Range -55°C to +125°C
Start Up Time 10mSec Maximum